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The following technique of open-loop oscillator design, as well as more LC and crystal oscillator topographies, can be found in further detail in the classic oscillator text by Randall W Rhea, Oscillator Design and Computer Simulation These design procedures, as popularized by both Rhea and R Matthys, have made oscillator design a simple and far more repeatable procedure than in the past Formally, it was either a horribly mathematically intensive procedure with an uncertain outcome or simply copying a particular oscillator design and empirically swapping out the frequency-determining components until the oscillator functioned as close as possible to the desired specifications

Open-loop design of an oscillator involves opening the feedback loop of the oscillator from the transistor s output, back to the resonant phase-shifting network (Fig 44), within our linear simulation software We then insert a software tool called a Bode plotter within this open loop After the software design and simulation of the oscillator is complete, the open loop will be closed, and a fully functioning oscillator will have been completed Much of the preliminary design optimization of an oscillator can be assisted by software programs, such as the included PUFF linear simulator, or the high-end Genesys simulator available from Eagleware Within these two programs we can display the gain and phase of a signal as it passes through the oscillator s open-loop circuits The tool that allows us to view this gain and phase is the Bode plotter (Fig 45) The Bode plotter inserts a reference signal into the input of a circuit while sweeping through a range of frequencies, and can be found in both a Spice and a linear simulator The signal that is placed into the circuit from the Bode plotter can be considered to be at zero gain and zero phase shift Thus, any gain either positive or negative or any phase shift that occurs to the Bode s original swept input frequency after it passes through the circuit will be read on the Bode plotter s window and displayed as frequency versus gain and frequency versus phase shift in dB and degrees, respectively This allows us to view what happens to a signal at the output of a circuit as the input of this same circuit is swept in frequency at a constant

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The first three options in the Welcome Screen are grouped together because they are the most commonly used New File tells Elements that you want to begin with a blank slate; Browse for File is used when you want to open an existing image or manage your image files; and the last of these three will interest you if you use a scanner or own a digital camera Elements can connect directly to them with the Connect to Camera or Scanner option (Browsing and importing images from these devices is discussed in 2)

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reversed biased, they will have a very high low-frequency input impedance, and are thus voltage controlled Junction field-effect transistors are also quite capable of receiving an input of up to several volts (compared to the bipolar transistor s few tenths of a volt), and create less internal noise than a BJT, but they display less voltage gain and more signal distortion As shown in Fig 124, the structure of a JFET is composed of a gate, a source, and a drain The JFET s terminals are voltage biased in such a way that the drain-to-source voltage (VDS) causes the source to be more negative than the drain This lets the drain current (ID) flow from the source to the drain through the N channel The JFET characteristic curves of Fig 125 readily indicate that a JFET is a normally on device when there is no bias voltage present at the gate This permits the maximum JFET current (IDSS) to flow from the source to the drain When the gate and source are presented with a negative voltage ( VGS), an area lacking charge carriers (the depletion region) starts to form within the JFET s N channel This N channel depletion region functions as an insulator; therefore, as the JFET becomes increasingly reverse biased and increasingly exhausted of any charge carriers, the N channel continues to be narrowed by this developing depletion region The channel s resistance rises, decreasing the JFET s current output into its load resistor, which lowers the device s output voltage across this resistor As the negative gate voltage of VGS is increased, the depletion region continues to widen, decreasing current flow even further but a point is ultimately reached where the channel is totally depleted of all majority carriers, and no more current flow is possible The voltage at which the current flow stops is referred to as VGS(OFF) In short, the VGS successfully controls the JFET s channel resistance, and thus its drain current However, it is important that the drain-to-source voltage VDS should be of a high enough amplitude to allow the JFET to operate within its linear region,.

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